Overview Of Huawei OptiX OSN 500
No Data FoundSpecification Of Huawei OptiX OSN 500
Huawei OptiX OSN 500 Datasheet
Huawei OptiX OSN 500 Specification
Huawei OptiX OSN 500 Specification |
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Dimensions |
44mm (H) x 442mm (W) x 220mm (D) |
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Switch capacity |
Packet: 7.2 Gbit/s and TDM: 21.25 Gbit/s (higher order), 5 Gbit/s (lower order) |
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Service slots |
3 slots |
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Supported interfaces |
Ethernet interface |
FE/GE |
SDH interface |
STM-1/4 |
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PDH interface |
E1/E3; T1/T3 |
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CES interface |
ATM/IMA E1, ch STM-1 |
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Networking Mode |
Supporting pure packet or SDH networking Supporting single-fiber bidirectional transmission |
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Power Supply |
P48V DC/ -60V DC, 220V AC/110V AC |
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Operation Environment |
Temperature  |
Long term: -5ºC ~ 45ºC Short term: -5ºC ~ 55ºC |
Relative Humidity |
Long term: 5% ~ 85% Short term: 5% ~ 95% |
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Ethernet Feature |
E-Line, E-LAN and QinQ MPLS-TP based VPWS and VPLS MS-PW ETH PWE3 IGMP Snooping v2 Blacklist, Broadcast packet suppression, ACL |
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QoS |
Hierarchical QoS scheduling and traffic shaping DiffServ mode based on traffic classification Simple traffic classification, complex traffic classification, per hop behavior (PHB), and ACL Committed access rate (CAR) PQ scheduling priority, weighted round robin (WRR) and PQ+WRR queuing Tail drop and weighted random early detection (WRED) Shaping based on port scheduling priority |
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OAM |
MPLS-TP OAM |
LSP/PW OAM: CC, LB, LT AIS, RDI LM, DM LCK, TST CSF |
Ethernet OAM |
ETH-CC, ETH-Loopback, ETH-Link Trace, Remote Loopback, Remote Fault Detection, RMON(RFC 2819) |
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Protection |
Equipment-level Protection |
power 1+1 backup |
MPLS-TP based networklevel Protection |
LSP/PW Linear protection, Ring protection Anti multifailure protection based on MS-PW LAG, MC-LAG, Dual-homing protection, LPT ERPS, MSTP |
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SDH based network-level Protection |
2 fiber MS-SP Ring 1+1/1:n (n<=5) Linear MSP,SNCP LAG, LPT, LCAS |
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Synchronization |
Both Ethernet and SDH networks supporting clock synchronization Supporting G.813, Synchronous Ethernet and IEEE 1588v2 synchronization Adaptive clock recovery (ACR) One external clock inputs/outputs (2 MHz or 2 Mbit/s) Two external time signals(1pps+TOD) |